In high speed integrated circuits, clocks are vital to accurately synchronize various components. For example, a pipeline analog-to-digital converter (ADC) may use two or more steps involving different subranges of resolution. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted to a finer resolution, and the results are combined in a last step. This type of ADC is fast, has a high resolution, and may consume a relatively small die size. In such an application, the clock edge which determines the comparator strobe instance should be positioned with a high degree of accuracy independent of process, voltage, and temperature (PVT) variations.
Methods for controlling the position of the clock edge (e.g., the clock delay) are known in the art. Several conventional methods exist to generate a clock delay. For example, an RC-type delay as shown in FIG. 1 acts by charging/discharging a capacitor 103 between inverters 101 and 102. Capacitor 103 often comprises a MOS capacitor, a metal fringing capacitor, or a metal-insulator-metal (MIM) capacitor. When a resistor 104 is used, it often comprises a polysilicon resistor. However, the capacitance of capacitor 103 and the resistance of resistor 104 are strongly dependant on process, voltage, and temperature (PVT) variations. For example, the capacitance can vary by as much as 20% over PVT variations.
Another conventional clock delay generator is the IC type, as shown in FIG. 2. An IC type clock delay generator generally comprises a current charging capacitor 201 followed by either an inverter 202 or a comparator 203. In this type of delay circuit, variation of the inverter 202 threshold voltage across PVT corners may introduce significant delay dispersion. With a comparator 203, the comparator offset needs to be controlled within a generally narrow range. To amplify small voltage differences, the comparator needs to have high gain, which means lower bandwidth, because the gain bandwidth is generally fixed for a given process. The propagation delay due to the resulting low bandwidth may introduce undesirable variations in the amount of delay produced.
Yet another conventional clock delay generator is the delay-locked loop (DLL), as shown in FIG. 3. A DLL is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an oscillator within the circuit. DLL 300 comprises a delay chain composed of many delay gates (e.g., inverters 301 to 3NN). The input of the chain is connected to the reference clock input 310. Such DLLs may be relatively complicated (and therefore consume a relatively large amount of space in an integrated circuit die) and are generally not power efficient enough for low power applications.
Therefore, it would be desirable to provide a low power clock delay with a high degree of accuracy, independent of process, voltage, and temperature (PVT) variations.